The Effect of Deep JFET and P-Well Implant of 1.2kV 4H-SiC MOSFETs

Abstract

1.2kV 4H-SiC MOSFETs with different junction depths of JFET and P-well regions were fabricated. For each JFET/P-well depth combination, channel lengths and JFET widths were also varied to compare specific on-resistance, breakdown voltage, and short-circuit withstand time. It was discovered that deep JFET structure provides low specific on-resistance (12% lower) with high breakdown voltage. On the other hand, MOSFETs with deep P-well result in high breakdown voltage with low leakage current even in shorter channel length (0.4 $\mu$ m). Moreover, trade-off relationship between Ron,sp and short-circuit withstand time is discussed for MOSFETs with different JFET widths and channel lengths; the deep JFET implant provides better trade-off relationship due to the feasibility of narrow JFET width. For the further improvement of trade-off relationship, MOSFETs with deep JFET and P-well implant are proposed. Lastly, the importance of high channel mobility for not only static characteristics but also short-circuit characteristics was investigated. The in-depth understanding of measured electrical characteristics was supported by 2D-device simulations.

Keywords

• 4H-SiC
• MOSFET
• deep JFET implant
• deep p-well implant
• 2D-simulation
• design consideration