Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Abstract

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a pre-determined leakage current suitable for low-voltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the on-resistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

Keywords

• Automatic optimization
• on-resistance
• power LDMOS
• RESURF
• scaling limits