Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

Zhanhang Chen; Haoliang Shan; Ziyi Ding; Xia Wu; Xiaolin Cen; Xiaoyu Ma; Wanling Deng; Junkai Huang

doi:10.1109/JEDS.2024.3477928

IEEE Journal of the Electron Devices Society (Jan 2024)

Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

Zhanhang Chen,
Haoliang Shan,
Ziyi Ding,
Xia Wu,
Xiaolin Cen,
Xiaoyu Ma,
Wanling Deng,
Junkai Huang

Affiliations

Zhanhang Chen: ORCiD; Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Haoliang Shan: ORCiD; Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Ziyi Ding: ORCiD; Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Xia Wu: Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Xiaolin Cen: Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Xiaoyu Ma: Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Wanling Deng: ORCiD; Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China
Junkai Huang: ORCiD; Department of Electronic Engineering, Key Laboratory of New Semiconductors and Devices of Guangdong Higher Education Institutes, Jinan University, Guangzhou, China

DOI: https://doi.org/10.1109/JEDS.2024.3477928
Journal volume & issue: Vol. 12
pp. 948 – 955

Abstract

Read online

A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.

Published in IEEE Journal of the Electron Devices Society

ISSN: 2168-6734 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245494

About the journal

Abstract

Keywords