Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Abstract

A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (VD) and gate (VG) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (ΔVT), linear (ΔIDLIN) and saturation (ΔIDSAT) drain current and charge pumping current (ΔICP), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycle-by-cycle simulation of various Ring Oscillator (RO) circuits.

Keywords

• HCD
• BTI
• self-heating
• MOSFET
• DEMOS
• FinFET