IEEE Journal of the Electron Devices Society (Jan 2022)

Application of e-Beam Voltage Contrast Technique for Overlay Improvement and Process Window Control in Multi-Patterning Interconnect Scheme

  • Linrong Yang,
  • Runling Li,
  • Ikai Hsu,
  • Haiqiong Zhang,
  • Jiadong Ren,
  • Wenzhan Zhou,
  • Linlin Sun,
  • Yawen Xue,
  • Wenchao Yang,
  • Ruilin Zhang,
  • Yefang Zhu,
  • Yan Zhang,
  • Guifeng Zhang,
  • Yingying Fu,
  • Shan Yin,
  • Yujie Jia,
  • Bo Yu,
  • Tomasz Brozek

DOI
https://doi.org/10.1109/JEDS.2022.3203125
Journal volume & issue
Vol. 10
pp. 870 – 875

Abstract

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Interconnect development for the new technology node requires coordinated efforts of multiple module teams working to co-optimize patterning and metallization solutions to meet performance and yield, and reliability targets. This paper presents the results of interconnect patterning optimization to improve overlay and process window control using a novel methodology, Design-for-Inspection™ (DFI). Using design-assisted voltage contrast measurement techniques, the method enables in-line test and monitoring of process induced overlay and CD variation of back-end-of line (BEOL) features built with litho-etch-litho-etch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned directly, other combination of metal line and via colors may have uncontrolled misalignment risking open or short failures. The paper shows how the complete metrology coverage of multi-color combinations between dual patterned via and dual patterned metal lines helps driving the improvement of overlay and process margins in 14nm technology. The optimized process margin for via opens enables higher yields and better reliability.

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