FinFET Performance Enhancement by Source/Drain Cavity Structure Optimization

Abstract

Fin field-effect transistor (FinFET) technology has been introduced to the mainstream complementary metal-oxide semiconductor (CMOS) manufacturing for low-power and high-performance applications. However, advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance. In this study, for the first time, we demonstrate methods of enhancing p-channel FinFET (pFET) performance on a fully integrated advanced FinFET platform via source/drain (S/D) cavity structure optimization. By modulating the cavity depth and proximity around the optimal reference point, we show that the trade-off between the S/D resistance and short channel effect, as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization. An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.

Keywords

• finfet performance
• parasitic resistance and capacitance
• source/drain cavity
• cavity implant