Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element

Abstract

A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits 7.24× shorter write delay (TWA) and 2.89× lower variability in TWA than that of 2T2R. Moreover, it exhibits 5.08 × /4.33× lower variability in TRA and 1.46 × 107 × /2.07× lower hold power (HPWR) dissipation than that of S6T/ 2T2R at VDD = 2 V. In addition, it exhibits tolerance to variations in Vth of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.

Keywords

• Nonvolatile memory
• RRAM
• memristor
• CNFET
• leakage power
• write delay