Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

Abstract

Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics as well as thermal performance are critical. Due to the dissimilar properties between chip and board, the reliability of WLCSP can be challenging. This article reports a reliability study of WLCSP using 45nm RFSOI technology for 5G RF applications. Dedicated test chips and boards were designed and used for board level reliability tests. The test vehicles passed bHAST and drop test, whereas it is found that temperature cycling on board (TCoB) is challenging for solder joint reliability in some cases. Thorough tests were carried out based on Kelvin test on specially designed individual bump and bump pair structures and developed fail criterion. Finite element modeling was adopted to simulate the reliability performance in different configurations. The impact on reliability performance from bump depopulation, die thickness, bump size, UBM to board pad alignment, and board wiring trace were thoroughly investigated. Based on comprehensive testing and deep understanding of the failure mechanisms, design optimizations for chip, board and interconnect were implemented. WLCSP reliability was significantly improved.

Keywords

• WLCSP
• 5G
• mm-wave
• board level reliability
• temperature cycling on board
• solder joint fatigue