Machine Learning-Based Compact Model Design for Reconfigurable FETs

Abstract

In integrated circuit design compact models are the abstraction layer which connects semiconductor physics and circuit simulation. Established compact models like BSIM provide a powerful platform for many kinds of conventional MOSFETs. However, novel device concepts like reconfigurable FETs (RFETs) come with a higher expressiveness. Due to their altered transport physics as compared to classical inversion mode MOSFETs those devices are hard to describe in a closed form expression by classical compact models. Table models bridge this gap for devices with novel features or materials, but circuit simulation becomes slow and inaccurate due to interpolation and convergence difficulties. Table model data can, however, be translated to closed form expressions, providing equation based models without the need for interpolation during simulation time. This work shows data driven approaches to generate compact models from biasing tables without physical analysis of the device behavior. Two automated modeling techniques are applied to a recently emerged RFET, forming a Verilog-A compact model for DC and transient simulation in Cadence Virtuoso. Drive current is implemented as a neural network, large enough to accurately predict behavior of a multi-gate device. The high dynamic range from $mA$ to $pA$ is covered by combining a linear model for high currents and a logarithmic model for low currents. For transient simulation precise models for electrode charges are essential. Here, symbolic regression provides human-readable closed form expressions which allow direct implementation in Verilog-A. The compact model approach is demonstrated with device data generated from a structural technology model (TCAD). However, the entire modeling flow can directly be used on real device measurements, if a technology model is unavailable or unpractical. We show that the presented machine learning based compact models show better convergence, more accurate predictions and faster simulation $(82$ to 308 times) in Cadence SPECTRE than simple table models generated from the same device.

Keywords

• Compact model
• reconfigurable FET