Built-In Bias Generation in Anti-Ferroelectric Stacks: Methods and Device Applications

Abstract

The discovery of ferroelectric (FE) properties in binary oxides has enabled CMOS compatible and scalable FE memories. Recently, we reported a simple approach to introduce non-volatility into state-of-the-art dynamic random-access memory stacks that show anti-FE (AFE) behavior. By employing a pair of electrodes with different work functions, a built-in bias is generated. Consequently, this bias modulates the energy potential of the AFE and enables two stable non-volatile states. Using this approach, a significant endurance improvement compared to hafnia-based FE memories can be obtained. In this paper, we investigate the possibility to bypass the usage of asymmetric workfunction electrodes. Using the interface-engineering approach, based on fixed charge or dipole formation, we show two additional methods for built-in bias generation within AFE layer stacks. By characterizing the film properties and performance of AFE capacitors, we compare and investigate retention and endurance of both work function-difference-based and interface-based AFE non-volatile memory. Finally, for the first time we present the concept of a binary oxide-based AFE tunnel junction that leverages both an interface and work function engineered AFE stack.

Keywords

• Anti-ferroelectric
• tunnel-junction
• non-volatile memory
• DRAM