Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation

Abstract

When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.

Keywords

• Electrostatic discharge (ESD)
• transmission line pulse (TLP)
• human body model (HBM)
• GaN
• enhancement-mode HEMT (E-HEMT)
• power-rail ESD clamp circuit